1. Field of the Invention
The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device provided with a thin film transistor formed on a substrate.
2. Description of the Related Art
A liquid crystal display device is known a liquid crystal display device is known in which a thin film transistor is formed on a substrate made of, for example, glass or quartz (Japanese Patent Unexamined Publication No. Hei. 5-150262, No. Hei. 5-257164, No. Hei. 10-70277, and so forth). The thin film transistor (hereinafter properly referred to as TFT) functions as a display electrode.
A conventional device of this kind, for example, a liquid crystal display device formed of a p-Si (polysilicon) thin film transistor, an a-Si (amorphous silicon) thin film transistor, or the like has a problem that such a phenomenon occurs that an off current of a pixel transistor is increased by light incident from the side of a substrate (a quartz substrate, and so forth) or scattered light incident from the opposite side of the substrate, and a pixel potential leaks. This phenomenon has a large tendency to occur especially in the case where the liquid crystal display device is used for a projector.
For the purpose of avoiding the phenomenon, in the related art, as shown in a plane structure of FIG. 1 and sectional structures of FIGS. 2 and 3, a metal layer made of, for example, (W) or its silicide which does not transmit light, is disposed as a light shielding film just under a pixel transistor. A peripheral portion of the light shielding film, for example, the metal layer is connected to a fixed potential of Vss, Vcom, or the like. Although not shown, for the purpose of blocking off scattered light incident from the opposite side of the substrate, contrary to FIGS. 2 and 3, there is such a case that a metal layer of, for example, (Ti) which does not transmit light, is disposed as a light shielding film just over a pixel transistor, and its peripheral portion is likewise connected to a fixed potential of Vss, Vcom, or the like.
However, in such a connection method of the metal layer in the related art, the delay of a gate line potential is caused by parasitic capacitance constituted by the metal layer of the light shielding film with the fixed potential and a gate line for controlling the pixel transistor, which is made of, for example, doped polysilicon (DOPOS). As a result, such disadvantage is caused that the contrast of a liquid crystal display is lowered, or uniformity is deteriorated.
The structure and the problem of the related art will be further explained with an example of a case where the light shielding film is disposed just under the pixel transistor and with reference to FIGS. 1 to 3. FIG. 1 is a view showing the related art in the plane structure of a portion including the metal layer forming the light shielding film and a data line, FIG. 2 is a sectional view taken along line A-A' of FIG. 1, and FIG. 3 is a sectional view taken along line C-C' of FIG. 1.
As shown in FIGS. 1 to 3, pixel transistors 22 and 24 are constituted by first silicon layers 21 and 23 made of, for example, undoped silicon formed on a substrate 10 (here, a quartz substrate), and a gate line 3 (i.e, a second silicon layer) made of, for example, DOPOS, in which a gate insulating film 31 made of, for example, SiO2 intervenes between them. As mentioned above, since it is necessary to shield the pixel transistors 22 and 24 against light, as shown in FIG. 2, a metal layer made of, for example, W or its silicide is provided as a light shielding film 1 at the side of the substrate 10 here. This light shielding film 1 is shown especially by fine dots in FIG. 1. As shown in the drawings, this light shielding film 1 is connected to a metal layer 7 made of, for example, aluminum (Al), having a fixed potential such as Vss or Vcom and the light shielding film 1 is formed just under or beneath the gate line 3 in the related art of this case. The gate line 3 and an additional capacitance line 4 are formed of a second silicon layer made of, for example, DOPOS, and are especially shown by oblique lines in FIG. 1.
As described above, in the related art, since the light shielding film 1 connected to the metal layer 7 with the fixed potential is formed close to the gate line 3, the delay of the gate line potential is caused by the parasitic capacitance formed to the metal layer 7 with the fixed potential and the gate line 3, and a problem resulting from this can occur.
In FIGS. 1 to 3, reference numeral 6 denotes a second contact; 8 denotes a first contact; 51 and 52 denote data lines made of, for example, Al; 9 denotes an opening portion; 11 denotes a first insulating layer made of, for example, TEOS--SiO2; 12 denotes a second insulating layer made of, for example, phosphorus-containing silicon glass (PSG); 13 denotes a third insulating layer made of, for example, PSG; 14 denotes a flattened film made of, for example, SOG; 15 denotes a transparent electrode layer made of, for example, ITO; 16 denotes a liquid crystal layer made of, for example, twisted nematic (TN) liquid crystal; 17 denotes an opposite substrate side transparent electrode layer made of, for example, ITO; and 18 denotes an opposite substrate made of, for example, quartz.